1. Field of the Invention
The present invention generally relates to fabrication of semiconductor integrated circuits. More specifically, the present invention relates to a method of fabricating interconnect structures in a semiconductor substrate processing system.
2. Description of the Related Art
Integrated circuits (IC) are manufactured by forming discrete semiconductor devices on a surface of a semiconductor substrate, such as a silicon (Si) wafer. A multi-level network of interconnect structures is then formed to interconnect the devices. Copper (Cu) is the wiring material of choice for interconnect structures of advanced IC devices having a high circuit density. In addition to superior electrical conductivity, copper is more resistant than aluminum (Al) to electromigration, a phenomenon that may destroy a thin film conductive line during IC operation.
In the semiconductor industry, much effort is spent in developing smaller IC devices with ever-increasing operating speeds. To increase the circuit density, a dual damascene technique may be used during fabrication of the IC devices. Then, to increase the operating speed of such a device, inter-metal dielectric (IMD) layers are formed using materials having dielectric constants less than 4.0. Such materials are generally referred to as low-k materials. The low-k materials generally comprise carbon-doped dielectrics, such as organic doped silicon glass (OSG), fluorine doped silicon glass (FSG), organic polymers, and the like.
An IC device comprises a plurality of interconnect structures that are separated from each other and the substrate by the IMD layers. Such structures are generally fabricated using a dual damascene technique that comprises forming an insulator layer (e.g., IMD layer) into which trenches and openings are etched to pattern the contact vias and the conductive lines. The copper is then used to fill (metallize) the trenches and openings in the IMD layer, forming vias and conductive lines, respectively. During the copper metallization process, an excess amount of copper may be deposited onto the substrate. The excess metal may be removed using a planarization process, e.g., chemical-mechanical polishing (CMP) process. After the planarization process, the next wiring layer may be formed on top of the IMD layer.
During fabrication of the interconnect structure, lithographic errors may result in misalignment between the positions of a contact hole and a trench of the structure. Additionally, mechanical stress, as well as chemically aggressive agents used during the planarization process, may cause the material of the IMD layer to erode, crack, or peel off. Such defects may render the interconnect structure to operate sub-optimally or not at all.
Therefore, there is a need in the art for an improved method of fabricating a dual damascene interconnect structure.